You may bring up to 4 pages (single-sided) or 2 pages (double-sided) of Verilog modules that you have written.  (This is your incentive to do the labs.)  You don't need the simulation files or implementation constraint files.

You will need a calculator for Test 1.

Practice Problems for Test 1

2.4, 2.5, 2.6, 2.7, 2.8, 2.9, 3.1, 3.5, 3.6, 3.7, 3.8a, 4.1, 5.1, 5.2, 5.3, 5.13, 5.23 (in 2nd ed.) which is 5.24 (in 3rd and 4th ed.), 6.1, 6.2, 6.3

Also know how to handle "don't care" outputs (not in textbook but covered in lecture).

Recognize that "if" can be conditioned on combined expressions, i.e., if (x==1 & y-z>w)....

This year, there will be hexadecimal as well as binary numbers.
 


2013 test              solutions

2014 test              solutions

2015 test (TT)     solutions

2015 test (MW)  solutions               

2016 test               solutions

2017 test (TT)      solutions

2017 test (MW)   solutions

2018 test (TT)       solutions

2018 test (MW)   solutions



Practice Problems for Test 2

7.1, 7.2, 7.3, 7.5, 7.6, 8.2, 8.3, 8.4, 8.5

For this year's text, think about going in the reverse order (from a Verilog module to a circuit).  Think about timing diagrams and the difference between output and latched output in a Moore machine.

2013 test              solutions

2014 test              solutions

2015 test (TT)     solutions

2015 test (MW)  solutions

2016 test               solutions

2017 test (TT)      solutions

2017 test (MW)   solutions

2018 test (TT)       solutions

2018 test (MW)   solutions