You may bring up to 4 pages (single-sided) or 2 pages (double-sided) of Verilog modules that you have written.  (This is your motivation to do the labs.)  You don't need the simulation files or implementation constraint files.

You will need a calculator for Test 1.

Practice Problems for Test 1

2.4, 2.5, 2.6, 2.7, 2.8, 2.9, 3.1, 3.5, 3.6, 3.7, 3.8a, 4.1, 5.1, 5.2, 5.3, 5.13, 5.23 (in 2nd ed.) which is 5.24 (in 3rd ed.), 6.1, 6.2, 6.3

Also know how to handle "don't care" outputs (not in textbook but covered in lecture). 

Also understand that XOR is x^y = ~x&y | x&~y, and XNOR is ~(x^y) = x&y | ~x&~y.

Also understand how an XOR is used in an adder/subtractor (Fig. 6.24, or https://en.wikipedia.org/wiki/Adder-subtractor).  I don't mean memorize the circuit; I mean, what is the XOR output as a function of the control input (E in Fig. 6.24, D in wikipedia)?

2013 test              solutions

2014 test              solutions

2015 test (TT)     solutions

2015 test (MW)  solutions               

2016 test               solutions


Practice Problems for Test 2

7.1, 7.2, 7.3, 7.5, 7.6, 8.2, 8.3, 8.4, 8.5

This year, expect a Moore machine. 

2013 test              solutions

2014 test              solutions

2015 test (TT)     solutions

2015 test (MW)  solutions

2016 test               solutions